Verilog Crash Course code / full_adder.v
Code Sample

full_adder.v

The Lesson 2 exercise, completed in Lesson 3, and reused in Lesson 7's ripple-carry adder. Original source: code/full_adder.v.

// 1-bit full adder, combinational.
// Started as the Lesson 2 port-list exercise, completed in Lesson 3,
// and reused as a building block in Lesson 7's ripple_adder.
module full_adder (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire sum,
    output wire cout
);

    assign sum  = a ^ b ^ cin;
    assign cout = (a & b) | (cin & (a ^ b));

endmodule

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