Eight short lessons that take Boolean logic, state machines, and binary arithmetic you already know and map them onto Verilog — the language, the mental model, and the handful of rules that cause almost every early bug.
The single biggest mental shift: Verilog describes hardware that all exists and runs at once, not a sequence of steps. Plus simulation vs. synthesis.
02Module interfaces, vectors, the wire/reg distinction (and why it's not what it sounds like), and Verilog's four-valued logic.
03assign and always @(*), the operators you'll actually use, and the classic latch-inference bug.
Flip-flops, reset styles, and the most consequential rule in practical Verilog — with a live demo of exactly how it breaks.
05The state diagrams you already know, mapped onto the three-block Verilog coding style, with a worked traffic-light example.
06Writing simulation-only code that drives and checks a design — clocks, stimulus, $display, and waveform dumps.
Reusable, resizable modules with parameter, and structural replication with generate — a loop that builds hardware, not one that runs.
Multiple drivers, stale sensitivity lists, signed/unsigned traps, a synthesizable-vs-simulation cheat sheet, and pointers past this course.
A short list of high-quality external tutorials, the canonical Cummings paper, and recommended YouTube channels.
GlossaryEvery term introduced across the eight lessons, alphabetically, linked back to where it's first explained.
A 2-to-1 multiplexer using the ternary operator.
Lesson 3A 1-bit full adder — the building block reused in Lesson 7.
Lesson 4The buggy register swap — blocking assignment, negative example.
Lesson 4The correct register swap — non-blocking assignment.
Lesson 5A three-state Moore FSM in the three-block coding style.
Lesson 6A testbench driving the traffic light FSM and printing results.
Lesson 7A parameterized ripple-carry adder built with a generate loop.