Verilog Crash Course code / mux2to1.v
Code Sample

mux2to1.v

Used in Lesson 3 — Combinational Logic. Original source: code/mux2to1.v.

// 2-to-1 multiplexer, combinational.
// Introduced in Lesson 3 (Combinational Logic).
module mux2 (
    input  wire       sel,   // 1-bit select
    input  wire [7:0] a,     // 8-bit data input, chosen when sel == 0
    input  wire [7:0] b,     // 8-bit data input, chosen when sel == 1
    output wire [7:0] y      // 8-bit data output
);

    assign y = sel ? b : a;

endmodule

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