The buggy half of the demo in Lesson 4 — Sequential Logic. Original source: code/reg_swap_blocking.v.
// Register "swap" using BLOCKING assignment -- this is the WRONG way to
// swap two registers on a clock edge. See Lesson 4 (Sequential Logic).
//
// Because '=' takes effect immediately, statement 2 reads the value
// statement 1 just wrote. Starting from a=1, b=2, both end up holding 2
// after the edge instead of swapping. Kept here deliberately as a
// negative example -- do not copy this pattern into real designs.
module reg_swap_blocking (
input wire clk,
output reg [7:0] a,
output reg [7:0] b
);
initial begin
a = 8'd1;
b = 8'd2;
end
always @(posedge clk) begin
a = b; // a becomes 2 immediately
b = a; // b reads the NEW a (2) -- swap fails, both become 2
end
endmodule