Verilog Crash Course code / traffic_light_tb.v
Code Sample · Testbench

traffic_light_tb.v

The testbench from Lesson 6 — Testbenches & Simulation, exercising traffic_light_fsm.v. Original source: code/traffic_light_tb.v.

// Testbench for traffic_light_fsm. See Lesson 6 (Testbenches & Simulation).
// Simulation-only: generates a clock, drives reset and tick, and prints
// the light outputs once per simulated traffic cycle.
`timescale 1ns/1ps

module traffic_light_tb;
    reg clk = 0;
    reg rst;
    reg tick;
    wire red, yellow, green;

    always #5 clk = ~clk;   // 10ns period

    traffic_light_fsm dut (
        .clk(clk), .rst(rst), .tick(tick),
        .red(red), .yellow(yellow), .green(green)
    );

    initial begin
        $dumpfile("traffic_light.vcd");
        $dumpvars(0, traffic_light_tb);

        rst = 1; tick = 0;
        @(posedge clk);
        rst = 0;

        repeat (6) begin
            @(posedge clk);
            tick = 1;
            @(posedge clk);
            tick = 0;
            $display("t=%0t  red=%b yellow=%b green=%b", $time, red, yellow, green);
        end

        $finish;
    end
endmodule

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