Every term introduced across the eight lessons, alphabetically. The "first seen" link takes you to where it's properly explained with context.
| Term | Meaning | First seen |
|---|---|---|
| ANSI-style ports | Module port declaration style where direction, type, and width are all given directly in the port list, instead of declared again inside the module body (non-ANSI style). | L2 |
| Asynchronous reset | A reset that forces a register to its reset value immediately, independent of the clock — implemented by adding or posedge rst to the always block's sensitivity. | L4 |
Blocking assignment (=) | An assignment that takes effect immediately; the next statement in the block sees the updated value. Correct for combinational always @(*) blocks; wrong for sequential ones. | L3, contrasted in L4 |
| Combinational logic | Logic whose output depends only on its current inputs, with no memory of past values. | L3 |
Concatenation ({a, b}) | An operator that glues signals together into one wider vector, most-significant operand first. | L3 |
| DUT (device under test) | The design being exercised by a testbench. | L6 |
| Edge-triggered | Reacting only at the instant a signal transitions (e.g. clock rising from 0 to 1), rather than continuously. | L4 |
| Elaboration | The compile-time step where parameters are resolved and generate loops are unrolled into concrete hardware, before simulation or synthesis proper begins. | L7 |
| Flip-flop | A single bit of edge-triggered memory — the fundamental sequential storage element, described in Verilog with a clocked always block. | L4 |
| Generate block | A generate ... endgenerate construct (often with a for loop over a genvar) that stamps out repeated hardware structure at elaboration time. | L7 |
| Genvar | A special integer type that exists only during elaboration, used to index a generate-for loop. Has no hardware representation. | L7 |
| Hardware Description Language (HDL) | A language for describing the structure and behavior of digital hardware, as opposed to a sequence of instructions for a processor to execute. | L1 |
| High-impedance (Z) | One of Verilog's four signal values, meaning a wire currently has no driver at all. | L2 |
| Instance / instantiation | A specific, physical copy of a module placed inside another module, with its own instance name. Distinct from a software function call — an instance permanently exists rather than being invoked and returned from. | L1, syntax in L2 |
| Latch (inferred) | Unintended level-sensitive memory that a synthesis tool must insert when a combinational always block fails to assign an output on every possible path. | L3 |
| Literal / radix | A sized number constant, written <size>'<radix><value>, e.g. 8'hFF. Radix is binary (b), hex (h), decimal (d), or octal (o). | L3 |
| Localparam | A named constant, like parameter, but one that instantiating code cannot override — used for a module's own internal constants (e.g. FSM state encodings). | L5, contrasted with parameter in L7 |
| Mealy machine | An FSM whose outputs depend on both the current state and the current input. | L5 |
| Module | Hardware's basic unit of structure: a named block with a fixed port interface and an internal implementation. The Verilog equivalent of a schematic symbol. | L1 |
| Moore machine | An FSM whose outputs depend only on the current state, not on the current input. | L5 |
| Multiple drivers | The error condition where more than one source (two assigns, or two always blocks) tries to drive the same signal, causing contention (often resolving to X) or an unreliable race. | L8 |
| Netlist | The output of synthesis: an explicit list of real gates/flip-flops and the wires connecting them, ready to be placed on an FPGA or fabricated as an ASIC. | L1 |
| Next-state logic | The combinational logic in an FSM that computes what the state register should become on the next clock edge. | L5 |
Non-blocking assignment (<=) | An assignment whose right-hand side is evaluated using pre-edge values and whose left-hand side updates only at the end of the current simulation time step — models real flip-flops correctly. Required for sequential always @(posedge clk) blocks. | L4 |
| Parameter | A named constant a module declares that instantiating code is allowed to override per-instance, enabling reusable, differently-sized copies of the same module. | L7 |
| Part-select | Selecting a contiguous range of bits from a vector, e.g. data[7:4]. | L2 |
| Port | A named input, output, or inout on a module's interface — the module's equivalent of a pin. | L2 |
| reg | A signal type that must be assigned procedurally (inside an always/initial block) and holds its value between assignments. Does not by itself imply the signal becomes a physical register — see Lesson 2. | L2 |
| Sensitivity list | The set of signals that trigger an always block to re-evaluate. Written automatically with @(*) for combinational logic, or explicitly for clocked logic (@(posedge clk)). | L3 |
| Simulator | A tool that executes a Verilog design as an event-driven program to check its behavior over time, before it's ever built as real hardware. | L1 |
| State register | The clocked reg in an FSM that holds the current state — the only actual memory element in the machine. | L5 |
| Synchronous reset | A reset that only takes effect on a clock edge, checked like any other input inside the clocked always block. | L4 |
| Synthesis / synthesis tool | The process (and tool) that converts synthesizable Verilog into a netlist of real gates and flip-flops for an FPGA or ASIC. | L1 |
| Synthesizable | Describing a construct that corresponds to real, buildable hardware, as opposed to simulation-only scaffolding. | L1, reference table in L8 |
| Testbench | Simulation-only code that instantiates a design, drives its inputs over simulated time, and checks or displays its outputs. Never synthesized. | L1, in depth in L6 |
| Unknown (X) | One of Verilog's four signal values, meaning undefined — either an uninitialized register or a genuine conflict between multiple drivers. | L2 |
| VCD file (Value Change Dump) | A file recording every signal's value changes over simulated time, produced by $dumpfile/$dumpvars and viewable as waveforms (e.g. in GTKWave). | L6 |
| Vector | A multi-bit signal declared with a bit range, e.g. [7:0], most-significant bit first. | L2 |
| wire | A signal type representing a passive connection with no memory of its own — must be continuously driven by an assign or a module output. | L2 |