Verilog Crash Course code / ripple_carry_adder_gen.v
Code Sample

ripple_carry_adder_gen.v

The generate example from Lesson 7 — Parameters & Generate Blocks, built from copies of full_adder.v. Original source: code/ripple_carry_adder_gen.v.

// Parameterized ripple-carry adder built from full_adder instances via
// a generate/for loop. See Lesson 7 (Parameters & Generate Blocks).
// Requires full_adder.v to be compiled alongside this file.
module ripple_adder #(
    parameter WIDTH = 4
) (
    input  wire [WIDTH-1:0] a, b,
    input  wire             cin,
    output wire [WIDTH-1:0] sum,
    output wire             cout
);
    wire [WIDTH:0] carry;
    assign carry[0] = cin;
    assign cout      = carry[WIDTH];

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin : adder_stage
            full_adder fa (
                .a    (a[i]),
                .b    (b[i]),
                .cin  (carry[i]),
                .sum  (sum[i]),
                .cout (carry[i+1])
            );
        end
    endgenerate
endmodule

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